Due to gradually reduced size of electronic products, semiconductor packages used in the electronic products are accordingly required having high density, high speed and low cost, such as flip-chip package; ball grid array (BGA) package, chip size package (CSP) and multi chip module (MCM) that become the mainstream packaging technology in the market.
For flip-chip package, BGA package, CSP and MCM, the build-up technology for fabricating circuit boards is popularized and cost-effective to implement, making the build-up circuit boards commonly employed in these high-density packages. The build-up circuit boards are suitably used in for example microprocessor modules, 3D graphics acceleration cards, single-chip BGA packages, expansion cards and MCM packages.
The build-up technology generally involves laminating a plurality of interlaced insulating and circuit layers on the surface of the circuit board, and then forming conductive vias in the insulating layers to electrically interconnect the conductive layers. The conductive vias are fabricated using the “plating filled copper” technology that allows via holes in the insulating layers to be filled with copper by plating, making the fabricated circuit board toward high-end development.
FIGS. 2A to 2E show the conventional plating-filled-copper process. Referring first to FIG. 2A, a circuit board 20 is prepared with an inner circuit layer 20a formed thereon.
Referring to FIG. 2B, a resin coated copper (RCC) layer 22 is pressed on the circuit board 20 and covers the inner circuit layer 20a. Alternatively, the RCC layer 22 can be made by forming an insulating layer on the circuit board 20 and then depositing an electroless-plated copper layer on the insulating layer.
Referring to FIG. 2C, a via hole 23 is fabricated through the RCC layer 22 by dry etching or wet etching to expose the inner circuit layer 20a. 
Referring to FIG. 2D, a conductive layer 24 is formed on the RCC layer 22, the inner wall of the via hole 23 and the exposed inner circuit layer 20a. 
Referring to FIG. 2E, finally, a resist layer 25 is pressed onto the conductive layer 24 and patterned to expose the via hole 23, so as to electroplate copper into the via hole 23 to form a conductive via 26.
As the depth of the via hole and the thickness of the insulating layer formed using the plated filled copper technique known in the prior art are significantly large as shown in FIG. 2E, the via hole 23 cannot be effectively filled up by an electroplating process. Therefore, the plated filled copper technique known in the prior art is unreliable and leads to no conduction or ineffective conduction of the build-up circuit board. The production yield of the build-up circuit board is dramatically reduced as the precision of the fabrication cannot be absolutely achieved.
However, since the insulating layer is relatively thick and the via hole is relatively deep, the above conventional plating-filled-copper process usually fails to completely fill the via hole with electroplated copper, such that the fabricated conductive via is not reliable and the electrical connection between the circuit layers in the circuit board through the conductive via may be defective, thereby degrading the production yield of the circuit board.
Moreover, since the above via hole is small and has a high aspect ratio, a superfilling copper-plating solution should be used as a filling agent to successfully fill the via hole with copper. On the other hand, a normal copper-plating solution (such as copper sulfate, sulfuric acid and hydrochloric acid) is not suitable for the above plating-filled-copper process. The superfilling copper-plating solution usually contains certain additives and thus is expensive in preparation, which thereby undesirably increases the fabrication cost.
Therefore, the problem to be solved here is to provide an improved circuit board structure and its fabrication method, which can avoid the above prior-art drawbacks so as to reduce the fabrication cost and assure the production yield.